HMN 2026: How Ferroelectric memory enables one chip to sample randomness and compute for generative AI

For the first time, a research team has demonstrated an artificial intelligence semiconductor technology that integrates the core functions of generative AI into a single device platform based on ferroelectric memory. This technology is significant as the first demonstration of implementing the two essential functions required for generative AI—random sampling and stable computation—within a single memory array.

The work is published in the journal Nature Communications. It was led by Professor Jong-Ho Lee of the Department of Electrical and Computer Engineering at Seoul National University College of Engineering.

The research team leveraged the properties of ferroelectric memory, which exhibits different electrical states depending on the applied voltage, to successfully implement both probabilistic sampling using random telegraph noise (RTN) and deterministic computation based on its ability to retain multiple electrical states even when power is turned off—all within a single platform.

One chip, two AI functions

Generative AI has recently been expanding rapidly into various domains, including image generation, video synthesis, autonomous systems and personalized content creation. However, implementing generative AI directly on semiconductor chips remains a significant challenge. Conventional AI semiconductors are primarily optimized for stable, deterministic computations such as classification and inference. In contrast, generative models additionally require probabilistic functions that sample random values from a latent space.

As a result, previous studies often separated probabilistic sampling and decoding into different devices or external software modules, leading to increased chip area, wiring complexity, power consumption and latency. In particular, integrating both functions within a single memory-based hardware platform while maintaining compatibility with conventional CMOS processes and scalability has remained a difficult challenge.

Using voltage to switch roles

To overcome these limitations, the research team focused on the voltage-dependent characteristics of hafnium oxide (HfO₂)-based ferroelectric memory. At higher voltage levels, strong random telegraph noise (RTN) emerges, enabling probabilistic sampling. At lower voltage levels, RTN is suppressed, allowing stable vector–matrix multiplication (VMM) computations based on nonvolatile multi-level conductance states. Through this approach, the team proposed a strategy to implement both randomness and stability required for generative AI within a single memory array.

This technology is particularly meaningful because it integrates sampling and decoding—previously separated functions in generative AI hardware—into a single ferroelectric memory-based platform. Notably, the same device can perform different roles depending on its operating regime without requiring additional external random number generators, thereby offering a pathway to improved integration density and power efficiency in future generative AI semiconductors.

From wafer test to image generation

The team experimentally validated the concept using a NOR-type ferroelectric memory array fabricated on a 15-centimeter (6-inch) wafer. By optimizing latent vector distributions through adjustments in voltage and sampling time, the system was applied to a variational autoencoder (VAE) for image generation using the CelebA face data set. The results demonstrated the capability to generate images reflecting diverse facial attributes. Furthermore, circuit-level validation confirmed that the generation performance remained stable even after approximately 100,000 repeated operations.

This study is considered a major milestone in generative AI hardware development, as it demonstrates that two previously separated functions can be integrated within a single ferroelectric memory-based device platform compatible with CMOS processes. The proposed AI semiconductor technology is expected to simultaneously improve both area and power efficiency in applications such as on-chip generative AI accelerators, neuromorphic systems and low-power edge AI semiconductors.

Path toward real-time hardware

In particular, the high compatibility of ferroelectric memory with existing semiconductor manufacturing processes opens up strong potential for scaling to large-scale generative AI hardware systems. The research team plans to further advance the technology toward real-time generative AI hardware by optimizing sampling speed, parallelism, array size and peripheral circuitry.

Lee, who led the study, stated, “Achieving both probabilistic sampling and deterministic computation simultaneously is a key challenge in generative AI hardware. This work is significant in that it demonstrates these two functions can be realized within a single device platform by leveraging the voltage-dependent characteristics of ferroelectric memory.”

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